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-- Company: 
-- Engineer: 
-- 
-- Create Date:    16:52:14 03/03/2012 
-- Design Name: 
-- Module Name:    RegFile - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity RegFile is
    Port ( 	
				rs1 : in  STD_LOGIC_VECTOR (2 downto 0);
				rs2 : in  STD_LOGIC_VECTOR (2 downto 0);
				rd : in  STD_LOGIC_VECTOR (2 downto 0);
				clk : in  STD_LOGIC;
				clr : in  STD_LOGIC;
				rf_sel : in  STD_LOGIC;
				w_sel : in STD_LOGIC;
				dataRegister_o : in  STD_LOGIC_VECTOR (7 downto 0);
				data_acc_o : in STD_LOGIC_VECTOR (7 downto 0);
				r1 : out STD_LOGIC_VECTOR (7 downto 0);
				r2 : out STD_LOGIC_VECTOR (7 downto 0)
			  );
end RegFile;

architecture Behavioral of RegFile is
	type regFile is array (7 downto 0) of STD_LOGIC_VECTOR (7 downto 0);
	signal regArray : regFile;
	shared variable regArr : regFile;
begin
	r1 <= regArray(conv_integer(rs1));
	r2 <= regArray(conv_integer(rs2));
	
	writeProcess : process (clk,w_sel,rd)								--ESCRITURA EN EL REGISTRO
	begin
		if falling_edge(clk) then
			if clr = '0' then
				regArr(7) := "00000000";
				regArr(6) := "00000000";
				regArr(5) := "00000000";
				regArr(4) := "00000000";
				regArr(3) := "00000000";
				regArr(2) := "00000000";
				regArr(1) := "00000000";
				regArr(0) := "00000000";
			elsif conv_integer(rd) > 0 then
				if rf_sel = '0' then  								--HABILITADA ESCRITURA
					if w_sel = '0' then 								--ESCRIBO EL CONTENIDO DEL DATA REGISTER
						regArr(conv_integer(rd)) := dataRegister_o;
					else													--ESCRIBO LO QUE HAY EN EL ACUMULADOR
						regArr(conv_integer(rd)) := data_acc_o;
					end if;
				end if;
			end if;
				regArray(7) <= regArr(7);
				regArray(6) <= regArr(6);
				regArray(5) <= regArr(5);
				regArray(4) <= regArr(4);
				regArray(3) <= regArr(3);
				regArray(2) <= regArr(2);
				regArray(1) <= regArr(1);
				regArray(0) <= regArr(0);
		end if;
	end process writeProcess;

--	readProcess : process (rs1, rs2)							--LECTURA DEL REGISTRO
--	begin
--		if (conv_integer(rs1)=0) then
--			r1 <= (others => '0');
--		else
--			r1 <= regArray(conv_integer(rs1));
--		end if;
--		if (conv_integer(rs2)=0) then
--			r2 <= (others => '0');
--		else
--			r2 <= regArray(conv_integer(rs2));
--		end if;
--	end process readProcess;
end Behavioral;

